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Total properties:
31
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Patent #:
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Issue Dt:
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02/16/1999
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Application #:
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08780643
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Filing Dt:
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01/08/1997
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Title:
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SEMICONDUCTOR DEVICE HAVING AN ELEVATED ACTIVE REGION FORMED IN AN OXIDE TRENCH AND METHOD OF MANUFACTURE THEREOF
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Patent #:
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Issue Dt:
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09/21/1999
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Application #:
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08861897
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Filing Dt:
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05/22/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INTERCONNECT IN A LOGIC CIRCUIT
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Patent #:
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Issue Dt:
|
07/20/1999
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Application #:
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08864489
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Filing Dt:
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05/28/1997
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Title:
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RUN-TO-RUN CONTROL PROCESS FOR CONTROLLING CRITICAL DIMENSIONS
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Patent #:
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Issue Dt:
|
06/15/1999
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Application #:
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08905686
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Filing Dt:
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08/04/1997
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Title:
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METHOD OF FORMING A CONTACT HOLE IN AN INTERLEVEL DIELECTRIC LAYER USING DUAL ETCH STOPS
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Patent #:
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Issue Dt:
|
11/28/2000
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Application #:
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08925821
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Filing Dt:
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09/05/1997
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Title:
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ELIMINATION OF RESIDUAL MATERIALS IN A MULTIPLE-LAYER INTERCONNECT STRUCTURE
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Patent #:
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Issue Dt:
|
01/04/2000
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Application #:
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08959591
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Filing Dt:
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10/29/1997
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Title:
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METHOD AND SYSTEM FOR PROVIDING AN INTERCONNECT HAVING REDUCED FAILURE RATES DUE TO VOIDS
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|
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Patent #:
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|
Issue Dt:
|
01/18/2000
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Application #:
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08959796
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Filing Dt:
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10/29/1997
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Title:
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METHOD OF MAKING GATE DIELECTRIC FOR SUB-HALF MICRON MOS TRANSISTORS INCLUDING A GRADED DIELECTRIC CONSTANT
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Patent #:
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Issue Dt:
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10/26/1999
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Application #:
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08986283
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Filing Dt:
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12/06/1997
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Title:
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SILICIDED SHALLOW JUNCTION TRANSISTOR FORMATION AND STRUCTURE WITH HIGH AND LOW BREAKDOWN VOLTAGES
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Patent #:
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Issue Dt:
|
07/20/1999
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Application #:
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08992431
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Filing Dt:
|
12/18/1997
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Title:
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BORDERLESS VIAS
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|
|
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Patent #:
|
|
Issue Dt:
|
05/02/2000
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Application #:
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08992537
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Filing Dt:
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12/17/1997
|
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Title:
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DUAL DAMASCENE PROCESS USING SACRIFICIAL SPIN-ON MATERIAL
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|
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Patent #:
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|
Issue Dt:
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09/19/2000
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Application #:
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08992952
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Filing Dt:
|
12/18/1997
|
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Title:
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LOCAL INTERCONNECTS FOR IMPROVED ALIGNMENT TOLERANCE AND SIZE REDUCTION
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Patent #:
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Issue Dt:
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03/28/2000
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Application #:
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08993286
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Filing Dt:
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12/18/1997
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Title:
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SEMICONDUCTOR DEVICE HAVING DUAL GATE ELECTRODE MATERIAL AND PROCESS OF FABRICATION THEREOF
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|
|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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08993830
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Filing Dt:
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12/18/1997
|
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Title:
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METHODS AND ARRANGEMENTS FOR IMPROVED SPACER FORMATION WITHIN A SEMICONDUCTOR DEVICE
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|
|
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Patent #:
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|
Issue Dt:
|
02/08/2000
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Application #:
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08993910
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Filing Dt:
|
12/18/1997
|
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Title:
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CORE CELL STRUCTURE AND CORRESPONDING PROCESS FOR NAND TYPE HIGH PERFORMANCE FLASH MEMORY DEVICE
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|
|
|
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Patent #:
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Issue Dt:
|
04/04/2000
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Application #:
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09002727
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Filing Dt:
|
01/05/1998
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Title:
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SELECTIVELY SIZED SPACERS
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|
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Patent #:
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|
Issue Dt:
|
08/01/2000
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Application #:
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09052051
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Filing Dt:
|
03/30/1998
|
|
Title:
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TRENCHED GATE METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD
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|
|
|
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Patent #:
|
|
Issue Dt:
|
11/14/2000
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Application #:
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09073639
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Filing Dt:
|
05/06/1998
|
|
Title:
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INTEGRATED CIRCUIT HAVING AN INTERLEVEL INTERCONNECT COUPLED TO A SOURCE/DRAIN REGION(S) WITH SOURCE/DRAIN REGION(S) BOUNDARY OVERLAP AND REDUCED PARASITIC CAPACITANCE
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|
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Patent #:
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|
Issue Dt:
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08/01/2000
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Application #:
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09102893
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Filing Dt:
|
06/23/1998
|
|
Title:
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HIGH INTEGRITY VIAS
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|
|
|
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Patent #:
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|
Issue Dt:
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11/27/2001
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Application #:
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09177871
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Filing Dt:
|
10/23/1998
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Title:
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ULTRATHIN, NITROGEN-CONTAINING MOSFET SIDEWALL SPACERS USING LOW-TEMPERATURE SEMICONDUCTOR FABRICATION PROCESS
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|
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Patent #:
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|
Issue Dt:
|
08/15/2000
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Application #:
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09187462
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Filing Dt:
|
11/04/1998
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING AN ELEVATED ACTIVE REGION
FORMED IN AN OXIDE TRENCH
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/04/2001
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Application #:
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09207562
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Filing Dt:
|
12/08/1998
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|
Publication #:
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Pub Dt:
|
11/29/2001
| | | | |
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Title:
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USE OF SILICON OXYNITRIDE ARC FOR METAL LAYERS
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|
|
|
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Patent #:
|
|
Issue Dt:
|
05/15/2001
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Application #:
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09260001
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Filing Dt:
|
03/02/1999
|
|
Title:
|
BORDERLESS VIAS
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/16/2001
|
Application #:
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09262130
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Filing Dt:
|
03/03/1999
|
|
Publication #:
|
|
Pub Dt:
|
08/16/2001
| | | | |
|
Title:
|
METHOD AND SYSTEM FOR PROVIDING ELECTRICAL INSULATION FOR LOCAL INTERCONNECT IN A LOGIC CIRCUIT
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2002
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Application #:
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09443647
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Filing Dt:
|
11/18/1999
|
|
Title:
|
CORE CELL STRUCTURE AND CORRESPONDING PROCESS FOR NAND TYPE PERFORMANCE FLASH MEMORY DEVICE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/08/2002
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Application #:
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09504895
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Filing Dt:
|
02/16/2000
|
|
Title:
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Semiconductor package with supported overhanging upper die
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|
|
|
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Patent #:
|
|
Issue Dt:
|
06/04/2002
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Application #:
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09515319
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Filing Dt:
|
02/29/2000
|
|
Title:
|
METHODS AND ARRANGEMENTS FOR INSULATING LOCAL INTERCONNECTS FOR IMPROVED ALIGNMENT TOLERANCE AND SIZE REDUCTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2002
|
Application #:
|
09532731
|
Filing Dt:
|
03/22/2000
|
|
Publication #:
|
|
Pub Dt:
|
11/29/2001
| | | | |
|
Title:
|
DUAL DAMASCENE PROCESS USING SACRIFICIAL SPIN-ON MATERIALS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/30/2002
|
Application #:
|
09567013
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Filing Dt:
|
05/09/2000
|
|
Title:
|
SEMICONDUCTOR DEVICE HAVING UNIFORM SPACERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
12/23/2003
|
Application #:
|
09574695
|
Filing Dt:
|
05/17/2000
|
|
Title:
|
TRENCHED GATE METAL OXIDE SEMICONDUCTOR DEVICE AND METHOD
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/14/2002
|
Application #:
|
09776012
|
Filing Dt:
|
02/01/2001
|
|
Title:
|
LOW DIELECTRIC CONSTANT ETCH STOP LAYERS IN INTEGRATED CIRCUIT INTERCONNECTS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/13/2007
|
Application #:
|
09908390
|
Filing Dt:
|
07/18/2001
|
|
Title:
|
RUN TO RUN CONTROL PROCESS FOR CONTROLLING CRITICAL DIMENSIONS
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|
