Patent Assignment Details
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
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| Reel/Frame: | 049937/0968 | |
| Pages: | 8 |
| | Recorded: | 08/02/2019 | | |
| Conveyance: | ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). |
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Total properties:
6
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Patent #:
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Issue Dt:
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10/09/2007
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Application #:
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10845688
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Filing Dt:
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05/13/2004
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Publication #:
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Pub Dt:
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11/25/2004
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Title:
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SEMICONDUCTOR DEVICE WITH INCREASED EFFECTIVE CHANNEL LENGTH AND METHOD OF MANUFACTURING THE SAME
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Patent #:
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Issue Dt:
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03/11/2008
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Application #:
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11656715
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Filing Dt:
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01/23/2007
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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METHOTHOLOGY FOR ESTIMATING STATISTICAL DISTRIBUTION CHARACTERISTICS OF PRODUCT PARAMETERS
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Patent #:
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Issue Dt:
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08/23/2011
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Application #:
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12335831
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Filing Dt:
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12/16/2008
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Publication #:
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Pub Dt:
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06/25/2009
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Title:
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METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A LAYER SUSPENDED ACROSS A TRENCH
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Patent #:
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Issue Dt:
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04/17/2012
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Application #:
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12348175
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Filing Dt:
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01/02/2009
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Publication #:
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Pub Dt:
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01/21/2010
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Title:
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PRINTED CIRCUIT BOARD FOR ACCOMPLISHING NARROW SCRIBE LANE AND SEMICONDUCTOR PACKAGE INCLUDING THE PRINTED CIRCUIT BOARD
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Patent #:
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Issue Dt:
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11/15/2011
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Application #:
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12754244
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Filing Dt:
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04/05/2010
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Publication #:
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Pub Dt:
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10/07/2010
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Title:
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METHODS OF FABRICATING RECESSED CHANNEL METAL OXIDE SEMICONDUCTOR (MOS) TRANSISTORS
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Patent #:
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Issue Dt:
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03/22/2016
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Application #:
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14258107
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Filing Dt:
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04/22/2014
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Publication #:
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Pub Dt:
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10/30/2014
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Title:
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SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
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Assignee
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| 8105 RASOR BOULEVARD, SUITE 210 |
| PLANO, TEXAS 75024 |
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Correspondence name and address
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KATANA SILICON TECHNOLOGIES LLC
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8105 RASOR BOULEVARD, SUITE 210
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PLANO, TX 75024
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