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Patent #:
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Issue Dt:
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04/23/1996
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Application #:
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08157358
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Filing Dt:
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11/23/1993
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Title:
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PSEUDO-NONVOLATILE MEMORY INCORPORATING DATA REFRESH OPERATION
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Patent #:
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Issue Dt:
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11/19/1996
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Application #:
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08165563
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Filing Dt:
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12/10/1993
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Title:
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WAFER SCALE INTEGRATED CIRCUIT INTERCONNECT STRUCTURE ARCHITECTURE
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Patent #:
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Issue Dt:
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03/12/1996
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Application #:
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08246396
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Filing Dt:
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05/20/1994
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Title:
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CIRCUIT MODULE REDUNDANCY ARCHITECTURE
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Patent #:
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Issue Dt:
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08/05/1997
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Application #:
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08270856
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Filing Dt:
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07/05/1994
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Title:
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RESYNCHRONIZATION CIRCUIT FOR A MEMORY SYSTEM AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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03/18/1997
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Application #:
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08307496
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Filing Dt:
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09/14/1994
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Title:
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METHOD AND CIRCUIT FOR COMMUNICATION BETWEEN A MODULE AND A BUS CONTROLLER IN A WAFER-SCALE INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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03/12/1996
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Application #:
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08417511
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Filing Dt:
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04/05/1995
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Title:
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REDUCED CMOS-SWING CLAMPING CIRCUIT FOR BUS LINES
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Patent #:
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Issue Dt:
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01/07/1997
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Application #:
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08469887
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Filing Dt:
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06/06/1995
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Title:
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DEFECT TOLERANT INTEGRATED CIRCUIT SUBSYSTEM FOR COMMUNICATION BETWEEN A MODULE AND A BUS CONTROLLER IN A WAFER-SCALE INTEGRATED CIRCUIT SYSTEM
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Patent #:
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Issue Dt:
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04/07/1998
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Application #:
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08473633
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Filing Dt:
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06/06/1995
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Title:
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RESYNCHRONIZATION CIRCUIT FOR CIRCUIT MODULE ARCHITECTURE
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Patent #:
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Issue Dt:
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07/28/1998
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Application #:
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08479915
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Filing Dt:
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06/07/1995
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Title:
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CACHING METHOD AND CIRCUIT FOR A MEMORY SYSTEM WITH CIRCUIT MODULE ARCHITECTURE
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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08484063
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Filing Dt:
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06/06/1995
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Title:
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FAULT-TOLERANT HIERARCHICAL BUS SYSTEM AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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03/25/1997
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Application #:
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08522032
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Filing Dt:
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08/31/1995
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Title:
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METHOD AND STRUCTURE FOR CONTROLLING INTERNAL OPERATIONS OF A DRAM ARRAY
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Patent #:
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Issue Dt:
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03/17/1998
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Application #:
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08549610
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Filing Dt:
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10/27/1995
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Title:
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TERMINATION CIRCUITS FOR REDUCED SWING SIGNAL LINES AND METHODS FOR OPERATING SAME
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Patent #:
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Issue Dt:
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08/04/1998
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Application #:
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08587379
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Filing Dt:
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01/16/1996
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Title:
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METHOD AND STRUCTURE FOR IMPROVING DISPLAY DATA BANDWIDTH IN A UNIFIED MEMORY ARCHITECTURE SYSTEM
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Patent #:
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Issue Dt:
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12/30/1997
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Application #:
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08610108
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Filing Dt:
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02/29/1996
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Title:
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METHOD AND STRUCTURE FOR GENERATING A BOOSTED WORD LINE VOLTAGE AND BACK BIAS VOLTAGE FOR A MEMORY ARRAY
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Patent #:
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Issue Dt:
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07/21/1998
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Application #:
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08679873
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Filing Dt:
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07/15/1996
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Title:
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METHOD AND STRUCTURE FOR PERFORMING PIPELINE BURST ACCESSES IN A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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11/03/1998
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Application #:
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08689431
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Filing Dt:
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08/09/1996
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Title:
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TERMINATION CIRCUIT WITH POWER-DOWN MODE FOR USE IN CIRCUIT MODULE ARCHITECTURE
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Patent #:
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Issue Dt:
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08/17/1999
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Application #:
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08757494
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Filing Dt:
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11/27/1996
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Title:
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METHOD AND APPARATUS FOR DRAM REFRESH USING MASTER, SLAVE AND SELF- REFRESH MODES
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Patent #:
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Issue Dt:
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01/13/1998
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Application #:
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08757866
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Filing Dt:
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11/27/1996
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Title:
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METHOD AND STRUCTURE FOR CONTROLLING INTERNAL OPERATIONS OF A DRAM ARRAY
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08767707
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Filing Dt:
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12/17/1996
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Title:
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MULTI-PORT DRAM CELL AND MEMORY SYSTEM USING SAME
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Patent #:
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Issue Dt:
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12/01/1998
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Application #:
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08782135
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Filing Dt:
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01/13/1997
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Title:
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CIRCUIT MODULE REDUNDANCY ARCHITECTURE PROCESS
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Patent #:
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Issue Dt:
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10/27/1998
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Application #:
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08812000
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Filing Dt:
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03/05/1997
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Title:
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METHOD AND STRUCTURE FOR IMPLEMENTING A CACHE MEMORY USING A DRAM ARRAY
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Patent #:
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Issue Dt:
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07/23/2002
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Application #:
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08820297
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Filing Dt:
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03/18/1997
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Title:
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METHOD FOR USING A LATCHED SENSE AMPLIFIER IN A MEMORY MODULE AS A HIGH-SPEED CACHE MEMORY
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Patent #:
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Issue Dt:
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09/08/1998
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Application #:
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08891124
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Filing Dt:
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07/10/1997
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Title:
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METHOD AND STRUCTURE FOR GENERATING A BOOSTED WORD LINE VOLTAGE AND BACK BIAS VOLTAFE FOR A MEMORY ARRAY
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Patent #:
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Issue Dt:
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10/03/2000
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Application #:
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08942254
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Filing Dt:
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10/01/1997
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Title:
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SYSTEM UTILIZING A DRAM ARRAY AS A NEXT LEVEL CACHE MEMORY AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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08/07/2001
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Application #:
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08960951
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Filing Dt:
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10/30/1997
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Title:
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DATA PROCESSING SYSTEM WITH MASTER AND SLAVE DEVICES AND ASYMMETRIC SIGNAL SWING BUS
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Patent #:
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Issue Dt:
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02/22/2000
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Application #:
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09037396
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Filing Dt:
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03/09/1998
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Title:
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METHOD AND APPARATUS FOR 1-T SCRAM COMPATIBLE MEMORY
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Patent #:
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Issue Dt:
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06/20/2000
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Application #:
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09076608
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Filing Dt:
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05/12/1998
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Title:
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METHOD AND STRUCTURE FOR CONTROLLING OPERATION OF A DRAM ARRAY
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09080893
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Filing Dt:
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05/18/1998
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Title:
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METHOD TO MINIMIZE MEMORY ACCESS TIME
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Patent #:
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Issue Dt:
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04/10/2001
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Application #:
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09133475
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Filing Dt:
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08/12/1998
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Title:
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METHOD AND APPARATUS FOR MAXIMIZING THE RANDOM ACCESS BANDWIDTH OF A MULTI-BANK DRAM IN A COMPUTER GRAPHICS SYSTEM
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09134488
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Filing Dt:
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08/14/1998
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Title:
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MEMORY CELL FOR DRAM EMBEDDED IN LOGIC
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Patent #:
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Issue Dt:
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09/25/2001
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Application #:
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09153099
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Filing Dt:
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09/14/1998
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Title:
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METHOD AND STRUCTURE FOR UTILIZING A DRAM ARRAY AS SECOND LEVEL CACHE MEMORY
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Patent #:
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Issue Dt:
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12/07/1999
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Application #:
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09165228
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Filing Dt:
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10/01/1998
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Title:
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METHOD AND APPARATUS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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06/13/2000
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Application #:
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09181840
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Filing Dt:
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10/27/1998
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Title:
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METHOD AND APPARATUS FOR INCREASING THE TIME AVAILABLE FOR REFRESH FOR 1-T SRAM COMPATIBLE DEVICES
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Patent #:
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Issue Dt:
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04/24/2001
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Application #:
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09234778
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Filing Dt:
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01/20/1999
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Title:
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METHOD AND APPARATUS FOR REFRESHING A SEMICONDUCTOR MEMORY USING IDLE MEMORY CYCLES
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Patent #:
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Issue Dt:
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11/27/2001
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Application #:
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09267228
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Filing Dt:
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03/12/1999
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Title:
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HIGH-SPEED READ-WRITE CIRCUITRY FOR SEMI-CONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09332757
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Filing Dt:
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06/14/1999
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Title:
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ON-CHIP WORD LINE VOLTAGE GENERATION FOR DRAM EMBEDDED IN LOGIC PROCESS
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Patent #:
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Issue Dt:
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07/02/2002
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Application #:
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09405607
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Filing Dt:
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09/24/1999
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Title:
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READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME
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Patent #:
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Issue Dt:
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09/24/2002
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Application #:
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09415032
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Filing Dt:
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10/07/1999
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Title:
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METHOD OF OPERATING A SYSTEM-ON-A-CHIP INCLUDING ENTERING A STANDBY STATE IN A NON-VOLATILE MEMORY WHILE OPERATING THE SYSTEM-ON-A-CHIP FROM A VOLATILE MEMORY
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09427383
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Filing Dt:
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10/25/1999
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Title:
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DRAM CELL FABRICATED USING A MODIFIED LOGIC PROCESS AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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12/11/2001
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Application #:
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09444002
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Filing Dt:
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11/19/1999
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Title:
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NON-VOLATILE MEMORY CELL AND METHODS OF FABRICATING AND OPERATING SAME
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Patent #:
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Issue Dt:
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05/21/2002
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Application #:
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09493781
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Filing Dt:
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01/28/2000
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Title:
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DYNAMIC ADDRESS MAPPING AND REDUNDANCY IN A MODULAR MEMORY DEVICE
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Patent #:
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Issue Dt:
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05/04/2004
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Application #:
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09503751
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Filing Dt:
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02/14/2000
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Title:
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METHOD AND APPARATUS FOR MEMORY REDUNDANCY WITH NO CRITICAL DELAY-PATH
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Patent #:
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Issue Dt:
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11/14/2000
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Application #:
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09517609
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Filing Dt:
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03/02/2000
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Title:
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Clock phase generator for controlling operation of a dram array
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Patent #:
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Issue Dt:
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06/22/2004
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Application #:
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09535656
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Filing Dt:
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03/23/2000
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Title:
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MEMORY ARRAY WITH READ/WRITE METHODS
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Patent #:
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Issue Dt:
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08/27/2002
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Application #:
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09568088
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Filing Dt:
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05/09/2000
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Title:
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HIGH-DENSITY RATIO-INDEPENDENT FOUR-TRANSISTOR RAM CELL FABRICATED WITH A CONVENTIONAL LOGIC PROCESS
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Patent #:
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07/03/2001
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Application #:
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09590943
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Filing Dt:
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06/09/2000
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Title:
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Method and apparatus for increasing the time available for internal refresh for 1-T SRAM compatible devices
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09618863
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Filing Dt:
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07/19/2000
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Title:
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Method and structure of ternary CAM cell in logic process
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Patent #:
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Issue Dt:
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07/10/2001
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Application #:
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09656882
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Filing Dt:
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09/07/2000
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Title:
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Method for generating a clock phase signal for controlling operation of a dram array
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Patent #:
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Issue Dt:
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04/09/2002
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Application #:
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09768908
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Filing Dt:
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01/23/2001
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Publication #:
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Pub Dt:
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07/12/2001
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Title:
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Single-Port multi-bank memory system having read and write buffers and method of operating same
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Patent #:
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Issue Dt:
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10/22/2002
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Application #:
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09772434
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Filing Dt:
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01/29/2001
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Publication #:
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Pub Dt:
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12/20/2001
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Title:
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REDUCED TOPOGRAPHY DRAM CELL FABRICATED USING A MODIFIED LOGIC PROCESS AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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12/17/2002
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Application #:
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09795750
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02/27/2001
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Publication #:
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Pub Dt:
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07/19/2001
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Title:
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METHOD AND APPARATUS FOR FORCING IDLE CYCLES TO ENABLE REFRESH OPERATIONS IN A SEMICONDUCTOR MEMORY
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Patent #:
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01/07/2003
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Application #:
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09846093
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04/30/2001
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Pub Dt:
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10/04/2001
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Title:
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METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING CLOCK DIVISION
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Patent #:
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Issue Dt:
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01/21/2003
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Application #:
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09851713
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05/08/2001
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Pub Dt:
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11/01/2001
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Title:
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APPARATUS FOR CONTROLLING DATA TRANSFER BETWEEN A BUS AND MEMORY ARRAY AND METHOD FOR OPERATING SAME
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Issue Dt:
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11/19/2002
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Application #:
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09903094
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07/10/2001
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Publication #:
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Pub Dt:
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11/08/2001
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Title:
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MEMORY MODULES WITH HIGH SPEED LATCHED SENSE AMPLIFIERS
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10/26/2004
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09948163
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09/06/2001
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01/24/2002
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Title:
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NON-VOLATILE MEMORY SYSTEM
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03/30/2004
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09963984
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09/25/2001
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02/07/2002
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Title:
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HIGH-SPEED READ-WRITE CIRCUITRY FOR SEMI-CONDUCTOR MEMORY DEVICES
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Patent #:
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Issue Dt:
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05/23/2006
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Application #:
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10003602
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11/14/2001
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05/15/2003
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Title:
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ERROR CORRECTING MEMORY AND METHOD OF OPERATING SAME
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09/10/2002
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Application #:
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10007334
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10/29/2001
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Publication #:
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Pub Dt:
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05/09/2002
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Title:
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READ/WRITE BUFFERS FOR COMPLETE HIDING OF THE REFRESH OF A SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SAME
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06/03/2003
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Application #:
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10033690
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11/02/2001
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Publication #:
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Pub Dt:
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07/18/2002
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Title:
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DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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11/25/2003
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Application #:
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10043386
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Filing Dt:
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01/11/2002
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Publication #:
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Pub Dt:
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05/09/2002
| | | | |
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Title:
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REDUCED TOPOGRAPHY DRAM CELL FABRICATED USING A MODIFIED LOGIC PROCESS AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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12/09/2003
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Application #:
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10095901
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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ONE-TRANSISTOR FLOATING-BODY DRAM CELL IN BULK CMOS PROCESS WITH ELECTRICALLY ISOLATED CHARGE STORAGE REGION
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Patent #:
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Issue Dt:
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02/03/2004
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Application #:
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10095984
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Filing Dt:
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03/11/2002
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Publication #:
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Pub Dt:
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09/11/2003
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Title:
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VERTICAL ONE-TRANSISTOR FLOATING-BODY DRAM CELL IN BULK CMOS PROCESS WITH ELECTRICALLY ISOLATED CHARGE STORAGE REGION
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Patent #:
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Issue Dt:
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03/16/2004
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Application #:
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10114282
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Filing Dt:
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04/03/2002
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Publication #:
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Pub Dt:
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08/08/2002
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Title:
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METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING MULTIPLE CLOCK DIVISION
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Patent #:
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Issue Dt:
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01/28/2003
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Application #:
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10165589
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Filing Dt:
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06/07/2002
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Publication #:
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Pub Dt:
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10/24/2002
| | | | |
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS
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Patent #:
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Issue Dt:
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08/31/2004
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Application #:
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10231800
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Filing Dt:
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08/28/2002
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Publication #:
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Pub Dt:
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01/02/2003
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Title:
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METHOD OF FABRICATING A DRAM CELL HAVING A THIN DIELECTRIC ACCESS TRANSISTOR AND A THICK DIELECTRIC STORAGE CAPACITOR
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Patent #:
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Issue Dt:
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04/06/2004
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Application #:
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10273442
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Filing Dt:
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10/15/2002
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Publication #:
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Pub Dt:
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03/13/2003
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Title:
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LATCHED SENSE AMPLIFIERS AS HIGH SPEED MEMORY IN A MEMORY SYSTEM
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Patent #:
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Issue Dt:
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06/15/2004
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Application #:
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10279363
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Filing Dt:
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10/23/2002
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Publication #:
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Pub Dt:
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02/27/2003
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Title:
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METHOD AND APPARATUS FOR COMPLETELY HIDING REFRESH OPERATIONS IN A DRAM DEVICE USING CLOCK DIVISION
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Patent #:
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Issue Dt:
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05/24/2005
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Application #:
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10300427
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Filing Dt:
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11/20/2002
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Publication #:
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Pub Dt:
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04/10/2003
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Title:
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METHOD AND APPARATUS FOR TEMPERATURE ADAPTIVE REFRESH IN 1T-SRAM COMPATIBLE MEMORY USING THE SUBTHRESHOLD CHARACTERISTICS OF MOSFET TRANSISTORS
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Patent #:
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Issue Dt:
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01/11/2005
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Application #:
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10355477
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Filing Dt:
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01/31/2003
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Publication #:
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Pub Dt:
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08/07/2003
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Title:
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NON-VOLATILE MEMORY CELL FABRICATED WITH SLIGHT MODIFICATION TO A CONVENTIONAL LOGIC PROCESS AND METHODS OF OPERATING SAME
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Patent #:
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Issue Dt:
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11/04/2003
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Application #:
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10374917
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Filing Dt:
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02/25/2003
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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06/01/2004
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Application #:
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10374956
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Filing Dt:
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02/25/2003
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Publication #:
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Pub Dt:
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08/14/2003
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Title:
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DRAM CELL HAVING A CAPACITOR STRUCTURE FABRICATED PARTIALLY IN A CAVITY AND METHOD FOR OPERATING SAME
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Patent #:
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Issue Dt:
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09/21/2004
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Application #:
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10377677
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Filing Dt:
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02/28/2003
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Publication #:
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Pub Dt:
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09/02/2004
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Title:
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METHOD AND APPARATUS FOR LENGTHENING THE DATA-RETENTION TIME OF A DRAM DEVICE IN STANDBY MODE
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Patent #:
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Issue Dt:
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04/01/2008
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Application #:
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10645861
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Filing Dt:
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08/20/2003
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Publication #:
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Pub Dt:
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02/24/2005
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Title:
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TRANSPARENT ERROR CORRECTING MEMORY
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Patent #:
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Issue Dt:
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07/05/2005
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Application #:
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10676695
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Filing Dt:
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09/30/2003
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Publication #:
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Pub Dt:
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04/01/2004
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Title:
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Method of fabricating a one transistor floating-body DRAM cell in bulk CMOS process with electrically isolated charge storage region
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Patent #:
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Issue Dt:
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11/15/2005
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Application #:
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10705112
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Filing Dt:
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11/10/2003
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Publication #:
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Pub Dt:
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06/03/2004
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Title:
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METHOD OF FABRICATING VERTICAL ONE-TRANSISTOR FLOATING-BODY DRAM CELL IN BULK CMOS PROCESS WITH ELECTRICALLY ISOLATED CHARGE STORAGE REGION
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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10800382
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Filing Dt:
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03/11/2004
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Publication #:
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Pub Dt:
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12/23/2004
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Title:
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ERROR DETECTION/CORRECTION METHOD
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Patent #:
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Issue Dt:
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04/17/2007
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Application #:
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10927157
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Filing Dt:
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08/25/2004
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Publication #:
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Pub Dt:
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02/03/2005
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Title:
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HIGH SPEED MEMORY SYSTEM
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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10997604
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Filing Dt:
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11/23/2004
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Publication #:
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Pub Dt:
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06/08/2006
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Title:
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PREDICTIVE ERROR CORRECTION CODE GENERATION FACILITATING HIGH-SPEED BYTE-WRITE IN A SEMICONDUCTOR MEMORY
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Patent #:
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Issue Dt:
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06/06/2006
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Application #:
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10999259
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Filing Dt:
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11/29/2004
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Publication #:
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Pub Dt:
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04/07/2005
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Title:
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NON-VOLATILE MEMORY CELL FABRICATED WITH SLIGHT MODIFICATION TO A CONVENTIONAL LOGIC PROCESS AND METHODS OF OPERATING SAME
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Patent #:
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Issue Dt:
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01/29/2008
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Application #:
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11050988
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Filing Dt:
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02/03/2005
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Publication #:
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Pub Dt:
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08/03/2006
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Title:
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FABRICATION PROCESS FOR INCREASED CAPACITANCE IN AN EMBEDDED DRAM MEMORY
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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11166856
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Filing Dt:
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06/24/2005
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Publication #:
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Pub Dt:
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12/28/2006
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Title:
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WORD LINE DRIVER FOR DRAM EMBEDDED IN A LOGIC PROCESS
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Patent #:
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Issue Dt:
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09/25/2007
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Application #:
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11221098
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Filing Dt:
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09/06/2005
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Publication #:
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Pub Dt:
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05/25/2006
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Title:
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TRANSPARENT ERROR CORRECTING MEMORY THAT SUPPORTS PARTIAL-WORD WRITE
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Patent #:
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Issue Dt:
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03/02/2010
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Application #:
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11262141
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Filing Dt:
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10/28/2005
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Publication #:
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Pub Dt:
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05/03/2007
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Title:
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NON-VOLATILE MEMORY IN CMOS LOGIC PROCESS
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Patent #:
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Issue Dt:
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06/24/2008
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Application #:
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11279382
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Filing Dt:
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04/11/2006
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Publication #:
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Pub Dt:
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10/25/2007
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Title:
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NON-VOLATILE MEMORY IN CMOS LOGIC PROCESS AND METHOD OF OPERATION THEREOF
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11341881
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Filing Dt:
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01/26/2006
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Publication #:
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Pub Dt:
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07/26/2007
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Title:
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Method to increase charge retention of non-volatile memory manufactured in a single-gate logic process
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Patent #:
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Issue Dt:
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06/03/2008
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Application #:
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11421986
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Filing Dt:
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06/02/2006
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Publication #:
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Pub Dt:
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12/06/2007
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
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Patent #:
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Issue Dt:
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05/12/2009
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Application #:
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11427785
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Filing Dt:
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06/29/2006
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Publication #:
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Pub Dt:
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01/03/2008
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Title:
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DUAL-PORT SRAM MEMORY USING SINGLE-PORT MEMORY CELL
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Patent #:
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Issue Dt:
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03/03/2009
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Application #:
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11534506
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Filing Dt:
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09/22/2006
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Publication #:
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Pub Dt:
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03/29/2007
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Title:
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SCALABLE EMBEDDED DRAM ARRAY
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Patent #:
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Issue Dt:
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11/04/2008
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Application #:
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11559870
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Filing Dt:
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11/14/2006
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Publication #:
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Pub Dt:
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05/17/2007
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Title:
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WORD LINE DRIVER FOR DRAM EMBEDDED IN A LOGIC PROCESS
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11566138
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Filing Dt:
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12/01/2006
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Publication #:
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Pub Dt:
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06/05/2008
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Title:
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Embedded Memory And Multi-Media Accelerator And Method Of Operating Same
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Patent #:
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NONE
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Issue Dt:
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Application #:
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11961667
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Filing Dt:
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12/20/2007
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Publication #:
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Pub Dt:
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04/24/2008
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Title:
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Fabrication Process For Increased Capacitance In An Embedded DRAM Memory
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Patent #:
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Issue Dt:
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04/05/2011
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Application #:
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12021229
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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METHOD TO INCREASE CHARGE RETENTION OF NON-VOLATILE MEMORY MANUFACTURED IN A SINGLE-GATE LOGIC PROCESS
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Patent #:
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Issue Dt:
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01/13/2009
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Application #:
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12021255
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
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Patent #:
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Issue Dt:
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04/21/2009
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Application #:
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12021264
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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12021280
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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06/12/2008
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
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Patent #:
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Issue Dt:
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12/15/2009
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Application #:
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12021286
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Filing Dt:
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01/28/2008
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Publication #:
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Pub Dt:
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08/07/2008
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Title:
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NON-VOLATILE MEMORY EMBEDDED IN A CONVENTIONAL LOGIC PROCESS AND METHODS FOR OPERATING SAME
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12043527
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Filing Dt:
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03/06/2008
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Publication #:
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Pub Dt:
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08/28/2008
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Title:
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Error Detection/Correction Method
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12045557
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Filing Dt:
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03/10/2008
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Publication #:
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Pub Dt:
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06/26/2008
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Title:
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Non-Volatile Memory In CMOS Logic Process
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Patent #:
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NONE
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Issue Dt:
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Application #:
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12045593
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Filing Dt:
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03/10/2008
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Publication #:
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Pub Dt:
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06/26/2008
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Title:
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Non-Volatile Memory In CMOS Logic Process
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Patent #:
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Issue Dt:
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09/07/2010
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Application #:
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12048170
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Filing Dt:
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03/13/2008
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Publication #:
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Pub Dt:
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07/03/2008
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Title:
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SCALABLE EMBEDDED DRAM ARRAY
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