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Total properties:
46
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Patent #:
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|
Issue Dt:
|
10/08/2019
|
Application #:
|
11704725
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Filing Dt:
|
02/09/2007
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|
Publication #:
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Pub Dt:
|
08/30/2007
| | | | |
|
Title:
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METHOD AND APPARATUS FOR SELECTING AMONG A PLURALITY OF INSTRUCTION SETS TO A MICROPROCESSOR
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
13751145
|
Filing Dt:
|
01/28/2013
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|
Publication #:
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Pub Dt:
|
02/13/2014
| | | | |
|
Title:
|
MULTI-STAGE REGISTER RENAMING USING DEPENDENCY REMOVAL
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/21/2017
|
Application #:
|
13964257
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Filing Dt:
|
08/12/2013
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|
Publication #:
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Pub Dt:
|
03/13/2014
| | | | |
|
Title:
|
DYNAMICALLY RESIZABLE CIRCULAR BUFFERS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/23/2017
|
Application #:
|
14153223
|
Filing Dt:
|
01/13/2014
|
|
Publication #:
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Pub Dt:
|
10/30/2014
| | | | |
|
Title:
|
CONTROL OF PRE-FETCH TRAFFIC
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2017
|
Application #:
|
14153240
|
Filing Dt:
|
01/13/2014
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|
Publication #:
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Pub Dt:
|
07/17/2014
| | | | |
|
Title:
|
FILL PARTITIONING OF A SHARED CACHE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/17/2017
|
Application #:
|
14169771
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Filing Dt:
|
01/31/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/18/2014
| | | | |
|
Title:
|
INDIRECT BRANCH PREDICTION
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/22/2016
|
Application #:
|
14189719
|
Filing Dt:
|
02/25/2014
|
|
Publication #:
|
|
Pub Dt:
|
09/11/2014
| | | | |
|
Title:
|
MIGRATION OF DATA TO REGISTER FILE CACHE
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|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/31/2017
|
Application #:
|
14340932
|
Filing Dt:
|
07/25/2014
|
|
Publication #:
|
|
Pub Dt:
|
04/16/2015
| | | | |
|
Title:
|
PRIORITIZING INSTRUCTIONS BASED ON TYPE
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14456873
|
Filing Dt:
|
08/11/2014
|
|
Publication #:
|
|
Pub Dt:
|
02/26/2015
| | | | |
|
Title:
|
Increasing The Efficiency of Memory Resources In a Processor
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|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14548041
|
Filing Dt:
|
11/19/2014
|
|
Publication #:
|
|
Pub Dt:
|
06/04/2015
| | | | |
|
Title:
|
Soft-Partitioning of a Register File Cache
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2018
|
Application #:
|
14572186
|
Filing Dt:
|
12/16/2014
|
|
Publication #:
|
|
Pub Dt:
|
06/25/2015
| | | | |
|
Title:
|
PROCESSOR WITH VIRTUALIZED INSTRUCTION SET ARCHITECTURE & METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/05/2020
|
Application #:
|
14589693
|
Filing Dt:
|
01/05/2015
|
|
Title:
|
HARDWARE VIRTUALIZED INPUT OUTPUT MEMORY MANAGEMENT UNIT
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/03/2018
|
Application #:
|
14598415
|
Filing Dt:
|
01/16/2015
|
|
Publication #:
|
|
Pub Dt:
|
07/23/2015
| | | | |
|
Title:
|
Stack Saved Variable Pointer Value Prediction
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14612069
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
|
Title:
|
Processors with Support for Compact Branch Instructions & Methods
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14612077
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
|
Title:
|
PROCESSOR WITH GRANULAR ADD IMMEDIATES CAPABILITY & METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/02/2020
|
Application #:
|
14612090
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/27/2015
| | | | |
|
Title:
|
MODELESS INSTRUCTION EXECUTION WITH 64/32-BIT ADDRESSING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/08/2020
|
Application #:
|
14612104
|
Filing Dt:
|
02/02/2015
|
|
Publication #:
|
|
Pub Dt:
|
08/13/2015
| | | | |
|
Title:
|
PROCESSOR SUPPORTING ARITHMETIC INSTRUCTIONS WITH BRANCH ON OVERFLOW & METHODS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
11/28/2017
|
Application #:
|
14715117
|
Filing Dt:
|
05/18/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/24/2016
| | | | |
|
Title:
|
TRANSLATION LOOKASIDE BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
02/20/2018
|
Application #:
|
14722292
|
Filing Dt:
|
05/27/2015
|
|
Publication #:
|
|
Pub Dt:
|
12/03/2015
| | | | |
|
Title:
|
Decoding Instructions That Are Modified By One Or More Other Instructions
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
09/24/2019
|
Application #:
|
14741738
|
Filing Dt:
|
06/17/2015
|
|
Publication #:
|
|
Pub Dt:
|
11/03/2016
| | | | |
|
Title:
|
Fault Tolerant Processor for Real-Time Systems
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/14/2018
|
Application #:
|
14798841
|
Filing Dt:
|
07/14/2015
|
|
Publication #:
|
|
Pub Dt:
|
01/14/2016
| | | | |
|
Title:
|
PROCESSOR ARRANGED TO OPERATE AS A SINGLE-THREADED (NX)-BIT PROCESSOR AND AS AN N-THREADED X-BIT PROCESSOR IN DIFFERENT MODES OF OPERATION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
14809187
|
Filing Dt:
|
07/25/2015
|
|
Publication #:
|
|
Pub Dt:
|
01/28/2016
| | | | |
|
Title:
|
Conditional Branch Prediction Using a Long History
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/23/2018
|
Application #:
|
14829458
|
Filing Dt:
|
08/18/2015
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2016
| | | | |
|
Title:
|
PROCESSORS AND METHODS FOR CACHE SPARING STORES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
14873027
|
Filing Dt:
|
10/01/2015
|
|
Publication #:
|
|
Pub Dt:
|
10/13/2016
| | | | |
|
Title:
|
Cache Operation in a Multi-Threaded Processor
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14919922
|
Filing Dt:
|
10/22/2015
|
|
Publication #:
|
|
Pub Dt:
|
04/28/2016
| | | | |
|
Title:
|
Apparatus and Method of Throttling Hardware Pre-fetch
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
14930740
|
Filing Dt:
|
11/03/2015
|
|
Publication #:
|
|
Pub Dt:
|
05/04/2017
| | | | |
|
Title:
|
Processors Supporting Endian Agnostic SIMD Instructions and Methods
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
14930913
|
Filing Dt:
|
11/03/2015
|
|
Publication #:
|
|
Pub Dt:
|
02/25/2016
| | | | |
|
Title:
|
METHOD AND APPARATUS FOR SCHEDULING THE ISSUE OF INSTRUCTIONS IN A MULTITHREADED PROCESSOR
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/26/2020
|
Application #:
|
14935579
|
Filing Dt:
|
11/09/2015
|
|
Publication #:
|
|
Pub Dt:
|
05/11/2017
| | | | |
|
Title:
|
Fetch Ahead Branch Target Buffer
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
10/29/2019
|
Application #:
|
15001628
|
Filing Dt:
|
01/20/2016
|
|
Publication #:
|
|
Pub Dt:
|
07/20/2017
| | | | |
|
Title:
|
Execution of Load Instructions in a Processor
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15079784
|
Filing Dt:
|
03/24/2016
|
|
Publication #:
|
|
Pub Dt:
|
09/28/2017
| | | | |
|
Title:
|
EXCEPTION HANDLING IN PROCESSOR USING BRANCH DELAY SLOT INSTRUCTION SET ARCHITECTURE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15092728
|
Filing Dt:
|
04/07/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2017
| | | | |
|
Title:
|
APPARATUS AND METHODS FOR OUT OF ORDER ITEM SELECTION AND STATUS UPDATING
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
05/12/2020
|
Application #:
|
15092915
|
Filing Dt:
|
04/07/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2017
| | | | |
|
Title:
|
PROCESSORS SUPPORTING ATOMIC WRITES TO MULTIWORD MEMORY LOCATIONS & METHODS
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15093404
|
Filing Dt:
|
04/07/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/12/2017
| | | | |
|
Title:
|
READ DISCARDS IN A PROCESSOR SYSTEM WITH WRITE-BACK CACHES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/16/2018
|
Application #:
|
15134510
|
Filing Dt:
|
04/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
08/11/2016
| | | | |
|
Title:
|
Prioritising of Instruction Fetching in Microprocessor Systems
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
03/06/2018
|
Application #:
|
15183365
|
Filing Dt:
|
06/15/2016
|
|
Publication #:
|
|
Pub Dt:
|
10/06/2016
| | | | |
|
Title:
|
SPECULATIVE LOAD ISSUE
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15205445
|
Filing Dt:
|
07/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2017
| | | | |
|
Title:
|
CHECK POINTING A SHIFT REGISTER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/17/2018
|
Application #:
|
15205555
|
Filing Dt:
|
07/08/2016
|
|
Publication #:
|
|
Pub Dt:
|
01/12/2017
| | | | |
|
Title:
|
CHECK POINTING A SHIFT REGISTER USING A CIRCULAR BUFFER
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
07/23/2019
|
Application #:
|
15281661
|
Filing Dt:
|
09/30/2016
|
|
Publication #:
|
|
Pub Dt:
|
03/30/2017
| | | | |
|
Title:
|
FETCH UNIT FOR PREDICTING TARGET FOR SUBROUTINE RETURN INSTRUCTIONS
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/19/2018
|
Application #:
|
15387394
|
Filing Dt:
|
12/21/2016
|
|
Publication #:
|
|
Pub Dt:
|
04/13/2017
| | | | |
|
Title:
|
PRIORITIZING INSTRUCTIONS BASED ON TYPE
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
01/02/2018
|
Application #:
|
15438000
|
Filing Dt:
|
02/21/2017
|
|
Publication #:
|
|
Pub Dt:
|
06/15/2017
| | | | |
|
Title:
|
Migration of Data to Register File Cache
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
06/11/2019
|
Application #:
|
15467073
|
Filing Dt:
|
03/23/2017
|
|
Publication #:
|
|
Pub Dt:
|
07/06/2017
| | | | |
|
Title:
|
SCHEDULING EXECUTION OF INSTRUCTIONS ON A PROCESSOR HAVING MULTIPLE HARDWARE THREADS WITH DIFFERENT EXECUTION RESOURCES
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/25/2020
|
Application #:
|
15488649
|
Filing Dt:
|
04/17/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
Control of Pre-Fetch Traffic
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15489975
|
Filing Dt:
|
04/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
08/03/2017
| | | | |
|
Title:
|
STACK POINTER VALUE PREDICTION
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
08/06/2019
|
Application #:
|
15624121
|
Filing Dt:
|
06/15/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/21/2017
| | | | |
|
Title:
|
Fetching Instructions in an Instruction Fetch Unit
|
|
|
|
|
Patent #:
|
NONE
|
Issue Dt:
|
|
Application #:
|
15633988
|
Filing Dt:
|
06/27/2017
|
|
Publication #:
|
|
Pub Dt:
|
12/28/2017
| | | | |
|
Title:
|
AES Hardware Implementation
|
|
|
|
|
Patent #:
|
|
Issue Dt:
|
04/16/2019
|
Application #:
|
15707059
|
Filing Dt:
|
09/18/2017
|
|
Publication #:
|
|
Pub Dt:
|
01/04/2018
| | | | |
|
Title:
|
INDIRECT BRANCH PREDICTION
|
|
