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Patent Assignment Details

NOTE:Results display only for issued patents and published applications. For pending or abandoned applications please consult USPTO staff.

Reel/Frame:	016547/0979			Pages:	8
		Recorded:	09/20/2005
Conveyance:	RETROACTIVE ASSIGNMENT AND QUITCLAIM

Total properties: 36

1

Patent #:	5801995	Issue Dt:	09/01/1998	Application #:	08241669	Filing Dt:	05/12/1994
Title:	OPTION SETTING CIRCUIT AND AN INTEGRATED CIRCUIT APPARATUS INCLUDING THE OPTION SETTING CIRCUIT

2

Patent #:	5574388	Issue Dt:	11/12/1996	Application #:	08542519	Filing Dt:	10/13/1995
Title:	EMULATION SYSTEM HAVING A SCALABLE MULTI-LEVEL MULTI-STAGE PROGRAMMABLE INTERCONNECT NETWORK

3

Patent #:	5777489	Issue Dt:	07/07/1998	Application #:	08542838	Filing Dt:	10/13/1995
Title:	FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED DEBUGGING FACILITIES

4

Patent #:	5754827	Issue Dt:	05/19/1998	Application #:	08542946	Filing Dt:	10/13/1995
Title:	METHOD AND APPARATUS FOR PERFORMING FULLY VISIBLE TRACING OF AN EMULATION

5

Patent #:	5790832	Issue Dt:	08/04/1998	Application #:	08639248	Filing Dt:	04/23/1996
Title:	METHOD AND APPARATUS FOR TRACING ANY NODE OF AN EMULATION

6

Patent #:	5907697	Issue Dt:	05/25/1999	Application #:	08688329	Filing Dt:	07/30/1996
Title:	EMULATION SYSTEM HAVING A SCALABLE MULTI-LEVEL MULTI-STAGE HYBRID PROGRAMMABLE INTERCONNECT NETWORK

7

Patent #:	5831866	Issue Dt:	11/03/1998	Application #:	08980419	Filing Dt:	11/26/1997
Title:	METHOD AND APPARATUS FOR REMOVING TIMING HAZARDS IN A CIRCUIT DESIGN

8

Patent #:	6057706	Issue Dt:	05/02/2000	Application #:	08985372	Filing Dt:	12/04/1997
Title:	FIELD PROGRAMMABLE GATE ARRAY WITH INTEGRATED DEBUGGING FACILITIES

9

Patent #:	5999725	Issue Dt:	12/07/1999	Application #:	09062240	Filing Dt:	04/17/1998
Title:	METHOD AND APPARATUS TRACING ANY NODE OF AN EMULATION

10

Patent #:	6336087	Issue Dt:	01/01/2002	Application #:	09122493	Filing Dt:	07/24/1998
Publication #:	US20010011212	Pub Dt:	08/02/2001
Title:	METHOD AND APPARATUS FOR GATE-LEVEL SIMULATION OF SYNTHESIZED REGISTER TRANSFER LEVEL DESIGN WITH SOURCE-LEVEL DEBUGGING

11

Patent #:	6240376	Issue Dt:	05/29/2001	Application #:	09127584	Filing Dt:	07/31/1998
Title:	METHOD AND APPARATUS FOR GATE-LEVEL SIMULATION OF SYNTHESIZED REGISTER TRANSFER LEVEL DESIGNS WITH SOURCE-LEVEL DEBUGGING

12

Patent #:	6301553	Issue Dt:	10/09/2001	Application #:	09184841	Filing Dt:	11/02/1998
Title:	METHOD AND APPARATUS FOR REMOVING TIMING HAZARDS IN A CIRCUIT DESIGN

13

Patent #:	6947882	Issue Dt:	09/20/2005	Application #:	09404920	Filing Dt:	09/24/1999
Title:	REGIONALLY TIME MULTIPLEXED EMULATION SYSTEM

14

Patent #:	6934674	Issue Dt:	08/23/2005	Application #:	09404923	Filing Dt:	09/24/1999
Title:	CLOCK GENERATION AND DISTRIBUTION IN AN EMULATION SYSTEM

15

Patent #:	6265894	Issue Dt:	07/24/2001	Application #:	09404925	Filing Dt:	09/24/1999
Title:	RECONFIGURABLE INTEGRATED CIRCUIT WITH INTEGRATED DEBUGGING FACILITIES FOR USE IN AN EMULATION SYSTEM

16

Patent #:	6647362	Issue Dt:	11/11/2003	Application #:	09405602	Filing Dt:	09/24/1999
Title:	EMULATION SYSTEM SCALING

17

Patent #:	6473726	Issue Dt:	10/29/2002	Application #:	09405659	Filing Dt:	09/24/1999
Title:	METHOD AND APPARATUS FOR CONCURRENT EMULATION OF MULTIPLE CIRCUIT DESIGNS ON AN EMULATION SYSTEM

18

Patent #:	6388465	Issue Dt:	05/14/2002	Application #:	09525210	Filing Dt:	03/14/2000
Title:	A RECONFIGURABLE INTEGRATED CIRCUIT WITH INTEGRATED DEBUGGING FACILITIES AND SCALABLE PROGRAMMABLE INTERCONNECT

19

Patent #:	6658636	Issue Dt:	12/02/2003	Application #:	09901780	Filing Dt:	07/09/2001
Publication #:	US20030009735	Pub Dt:	01/09/2003
Title:	CROSS FUNCTION BLOCK PARTITIONING AND PLACEMENT OF A CIRCUIT DESIGN ONTO RECONFIGURABLE LOGIC DEVICES

20

Patent #:	7130788	Issue Dt:	10/31/2006	Application #:	10003184	Filing Dt:	10/30/2001
Publication #:	US20040034841	Pub Dt:	02/19/2004
Title:	EMULATION COMPONENTS AND SYSTEM INCLUDING DISTRIBUTED EVENT MONITORING, AND TESTING OF AN IC DESIGN UNDER EMULATION

21

Patent #:	7035787	Issue Dt:	04/25/2006	Application #:	10003951	Filing Dt:	10/30/2001
Publication #:	US20040078187	Pub Dt:	04/22/2004
Title:	EMULATION COMPONENTS AND SYSTEM INCLUDING DISTRIBUTED ROUTING AND CONFIGURATION OF EMULATION RESOURCES

22

Patent #:	6717433	Issue Dt:	04/06/2004	Application #:	10086813	Filing Dt:	02/28/2002
Publication #:	US20020089349	Pub Dt:	07/11/2002
Title:	RECONFIGURABLE INTEGRATED CIRCUIT WITH INTEGRATED DEBUGGING FACILITIES AND SCALABLE PROGRAMMABLE INTERCONNECT

23

Patent #:	6876962	Issue Dt:	04/05/2005	Application #:	10273700	Filing Dt:	10/18/2002
Publication #:	US20030055622	Pub Dt:	03/20/2003
Title:	METHOD AND APPARATUS FOR CONCURRENT EMULATION OF MULTIPLE CIRCUIT DESIGNS ON AN EMULATION SYSTEM

24

Patent #:	NONE	Issue Dt:		Application #:	10428917	Filing Dt:	05/05/2003
Publication #:	US20040225489	Pub Dt:	11/11/2004
Title:	Integrated self-testing of a reconfigurable interconnect

25

Patent #:	8099273	Issue Dt:	01/17/2012	Application #:	10454818	Filing Dt:	06/05/2003
Publication #:	US20040249623	Pub Dt:	12/09/2004
Title:	COMPRESSION OF EMULATION TRACE DATA

26

Patent #:	7286976	Issue Dt:	10/23/2007	Application #:	10458176	Filing Dt:	06/10/2003
Publication #:	US20040254780	Pub Dt:	12/16/2004
Title:	EMULATION OF CIRCUITS WITH IN-CIRCUIT MEMORY

27

Patent #:	NONE	Issue Dt:		Application #:	10460701	Filing Dt:	06/12/2003
Publication #:	US20040254778	Pub Dt:	12/16/2004
Title:	Reconfigurable logic element with input swapping

28

Patent #:	NONE	Issue Dt:		Application #:	10602020	Filing Dt:	06/24/2003
Publication #:	US20040267489	Pub Dt:	12/30/2004
Title:	Data compaction and pin assignment

29

Patent #:	7693703	Issue Dt:	04/06/2010	Application #:	10631824	Filing Dt:	08/01/2003
Publication #:	US20050027505	Pub Dt:	02/03/2005
Title:	CONFIGURATION OF RECONFIGURABLE INTERCONNECT PORTIONS

30

Patent #:	7098688	Issue Dt:	08/29/2006	Application #:	10668236	Filing Dt:	09/24/2003
Publication #:	US20040075469	Pub Dt:	04/22/2004
Title:	REGIONALLY TIME MULTIPLEXED EMULATION SYSTEM

31

Patent #:	7587649	Issue Dt:	09/08/2009	Application #:	10673211	Filing Dt:	09/30/2003
Publication #:	US20050071716	Pub Dt:	03/31/2005
Title:	TESTING OF RECONFIGURABLE LOGIC AND INTERCONNECT SOURCES

32

Patent #:	7305633	Issue Dt:	12/04/2007	Application #:	10736908	Filing Dt:	12/17/2003
Publication #:	US20040260530	Pub Dt:	12/23/2004
Title:	DISTRIBUTED CONFIGURATION OF INTEGRATED CIRCUITS IN AN EMULATION SYSTEM

33

Patent #:	7093174	Issue Dt:	08/15/2006	Application #:	10782410	Filing Dt:	02/17/2004
Publication #:	US20050193295	Pub Dt:	09/01/2005
Title:	TESTER CHANNEL COUNT REDUCTION USING OBSERVE LOGIC AND PATTERN GENERATOR

34

Patent #:	7158403	Issue Dt:	01/02/2007	Application #:	10791834	Filing Dt:	03/04/2004
Publication #:	US20050195642	Pub Dt:	09/08/2005
Title:	TERNARY BIT LINE SIGNALING

35

Patent #:	NONE	Issue Dt:		Application #:	10806235	Filing Dt:	03/23/2004
Publication #:	US20040178820	Pub Dt:	09/16/2004
Title:	Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect

36

Patent #:	7698118	Issue Dt:	04/13/2010	Application #:	10824489	Filing Dt:	04/15/2004
Publication #:	US20050234692	Pub Dt:	10/20/2005
Title:	LOGIC DESIGN MODELING AND INTERCONNECTION

Assignors

1

META SYSTEMS SARL

Exec Dt:

08/26/2005

2

Exec Dt:

08/26/2005

3

LEPAPE, OLIVIER

Exec Dt:

08/26/2005

4

REBLEWSKI, FREDERIC

Exec Dt:

08/26/2005

5

Exec Dt:

08/26/2005

6

Exec Dt:

08/26/2005

7

EMIRIAN, FREDERIC M.

Exec Dt:

08/26/2005

8

HOCHAPFEL, ERIC G.F.

Exec Dt:

08/26/2005

9

DOUEZY, FRANCOIS

Exec Dt:

08/26/2005

10

SAINT GENIEYS, DAVID FENECH

Exec Dt:

08/26/2005

11

LAURENT, GILLES

Exec Dt:

08/26/2005

12

SELVIDGE, CHARLEY

Exec Dt:

08/26/2005

13

DAVIS, ROBERT W.

Exec Dt:

08/26/2005

14

SCHMITT, PEER G.

Exec Dt:

08/26/2005

15

MARANTZ, JOSHUA D.

Exec Dt:

08/26/2005

16

DIEHL, PHILIPPE

Exec Dt:

08/26/2005

17

QUENNESSON, CYRIL

Exec Dt:

08/26/2005

18

FILOCHE, OLIVIER

Exec Dt:

08/26/2005

19

MONTAGNE, XAVIER

Exec Dt:

08/26/2005

20

BEDOISEAU, FLORENT

Exec Dt:

08/26/2005

21

MAQUINON, FRANCK

Exec Dt:

08/26/2005

22

JOSSO, FREDERIC

Exec Dt:

08/26/2005

Assignees

1

MENTOR GRAPHICS CORPORATION

8005 SW BOECKMAN ROAD

WILSONVILLE, OREGON 97070-7777

2

MENTOR GRAPHICS (HOLDING) LTD.

8005 SW BOECKMAN DRIVE

WILSONVILLE, OREGON 97070-7777

Correspondence name and address
	BANNER & WITCOFF, LTD.
	ELEVENTH FLOOR, 1001 G. STREET, N.W.
	WASHINGTON, DC 20001-4597

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