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Reel/Frame:018852/0983   Pages: 6
Recorded: 02/05/2007
Attorney Dkt #:11047 FEP/ALD
Conveyance: ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Total properties: 1
1
Patent #:
Issue Dt:
10/13/2009
Application #:
11496411
Filing Dt:
07/31/2006
Publication #:
Pub Dt:
01/31/2008
Title:
METHOD FOR FABRICATING AN INTEGRATED GATE DIELECTRIC LAYER FOR FIELD EFFECT TRANSISTORS
Assignors
1
Exec Dt:
07/28/2006
2
Exec Dt:
10/04/2000
3
Exec Dt:
07/28/2006
4
Exec Dt:
07/28/2006
5
Exec Dt:
07/27/2006
6
Exec Dt:
07/27/2006
7
Exec Dt:
07/27/2006
Assignee
1
P.O. BOX 450-A
LEGAL AFFAIRS DEPARTMENT
SANTA CLARA, CALIFORNIA 95052
Correspondence name and address
APPLIED MATERIALS, INC.
P.O. BOX 450-A
LEGAL AFFAIRS DEPT.
SANTA CLARA, CA 95052

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