Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/31/2018
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Application #:
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15182338
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Filing Dt:
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06/14/2016
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Inventors:
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Pawan Kulshreshtha, Amit Dhuria
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Title:
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HIERARCHICAL TIMING ANALYSIS FOR MULTI-INSTANCE BLOCKS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2655 SEELY AVENUE |
SAN JOSE, CALIFORNIA 95134 |
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SLW / CADENCE DESIGN SYSTEMS |
P.O. BOX 2938 |
MINNEAPOLIS, MN 55402 |
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