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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
Issue Dt:
11/13/2018
Application #:
15485062
Filing Dt:
04/11/2017
Publication #:
Pub Dt:
10/26/2017
Inventors:
Muraleedharan Ramakrishnan, Bhoodev Kumar, Vivek Oppula, Niju Alex Geevarughese
Title:
SYNCHRONOUS, INTERNAL CLOCK EDGE ALIGNMENT FOR INTEGRATED CIRCUIT TESTING
Assignment: 1
Reel/Frame:
047116/0655Recorded: 10/10/2018Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignor:
Exec Dt:
04/07/2015
Assignee:
800 WEST 6TH STREET
AUSTIN, TEXAS 78701
Correspondent:
TERRILE, CANNATTI & CHAMBERS, LLP
P.O. BOX 203518
AUSTIN, TX 78720
Assignment: 2
Reel/Frame:
042135/0671Recorded: 04/25/2017Pages: 4
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
04/18/2017
Exec Dt:
04/18/2017
Exec Dt:
04/18/2017
Exec Dt:
04/18/2017
Assignee:
7B NIGHTINGALE WAY, QUARTERMILE
EDINBURGH, UNITED KINGDOM EH3 9EG
Correspondent:
TERRILE, CANNATTI, CHAMBERS & HOLLAND, LLP
P.O. BOX 203518
AUSTIN, TX 78720

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