Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
10/01/2019
|
Application #:
|
15248093
|
Filing Dt:
|
08/26/2016
|
|
Publication #:
|
|
Pub Dt:
|
12/15/2016
| | | | |
|
Inventors:
|
Hsien-Hsin Sean Lee, Yun-Han Lee, William Wu Shen
|
|
Title:
|
Memory Circuit and Cache Circuit Configuration
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| NO. 8, LI-HSIN RD. 6 |
| SCIENCE-BASED INDUSTRIAL PARK |
| HSIN-CHU, TAIWAN 300-77 |
|
|
|
|
| HAYNES AND BOONE, LLP IP SECTION |
| 2323 VICTORY AVENUE |
| SUITE 700 |
| DALLAS, TX 75219 |
|
|
Search Results as of:
05/09/2024 09:21 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
