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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
01/14/2020
Application #:
15933949
Filing Dt:
03/23/2018
Publication #:
Pub Dt:
09/26/2019
Inventors:
Choonghyun Lee, Ruqiang Bao, Gen Tsutsui, Dechao Guo
Title:
GATE STACK DESIGNS FOR ANALOG AND LOGIC DEVICES IN DUAL CHANNEL SI/SIGE CMOS
Assignment: 1
Reel/Frame:
045328/0210Recorded: 03/23/2018Pages: 6
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
03/19/2018
Exec Dt:
03/19/2018
Exec Dt:
03/19/2018
Exec Dt:
03/19/2018
Assignee:
NEW ORCHARD ROAD
ARMONK, NEW YORK 10504
Correspondent:
MICHAEL J. CHANG
84 SUMMIT AVENUE
MICHAEL J. CHANG, LLC
MILFORD, CT 06460

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