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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
Issue Dt:
01/21/2020
Application #:
15171531
Filing Dt:
06/02/2016
Publication #:
Pub Dt:
12/07/2017
Inventors:
Sandeep Kumar GOEL, Saman M.I. ADHAM, Yun-Han LEE, Marat GERSHOIG
Title:
SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
Assignment: 1
Reel/Frame:
039377/0263Recorded: 08/09/2016Pages: 10
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
Exec Dt:
08/04/2016
Exec Dt:
08/04/2016
Exec Dt:
08/03/2016
Exec Dt:
08/03/2016
Assignee:
NO. 8, LI-HSIN ROAD 6
HSINCHU SCIENCE PARK
HSIN-CHU, TAIWAN 300-77
Correspondent:
DUANE MORRIS LLP
30 SOUTH 17TH STREET
PHILADELPHIA, PA 19103

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