Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/18/2020
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Application #:
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15896696
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Filing Dt:
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02/14/2018
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Publication #:
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Pub Dt:
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08/15/2019
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Inventors:
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Hao Nong, Liang Li, Chiew Wah Yap, Yung Fu Chong, Yun Ling Tan, Ting Huo
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Title:
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METHODS OF FORMING INTEGRATED CIRCUITS WITH SOLUTIONS TO INTERLAYER DIELECTRIC VOID FORMATION BETWEEN GATE STRUCTURES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 60 WOODLANDS INDUSTRIAL PARK D STREET 2 |
| SINGAPORE, SINGAPORE 738406 |
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| LKGLOBAL (GF) |
| 7010 E. COCHISE RD. |
| SCOTTSDALE, AZ 85253 |
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