Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/16/2021
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Application #:
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16509773
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Filing Dt:
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07/12/2019
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Publication #:
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Pub Dt:
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10/31/2019
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Inventors:
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Robert J. ALLEN, Vasant RAO, Xin ZHAO, Yanai DANAN, Jeffrey P. SOREFF
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Title:
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MODEL ORDER REDUCTION IN TRANSISTOR LEVEL TIMING
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| NEW ORCHARD ROAD |
| ARMONK, NEW YORK 10504 |
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| ANDREW M. CALDERON |
| 7918 JONES BRANCH DRIVE, SUITE 500 |
| MCLEAN, VA 22102 |
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