Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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12/27/2022
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Application #:
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17317482
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Filing Dt:
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05/11/2021
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Publication #:
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Pub Dt:
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01/26/2023
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Inventors:
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Rafael Rios, Sasikanth Manipatruni, Ikenna Odinaka, Rajeev Kumar Dokania et al
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Title:
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MAJORITY LOGIC GATE WITH INPUT PARAELECTRIC CAPACITORS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 180 STEUART STREET |
| #19254 |
| SAN FRANCISCO, CALIFORNIA 94105 |
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| MUGHAL IP P.C. |
| 1500 NW BETHANY BLVD. |
| SUITE 200 |
| BEAVERTON, OR 97006 |
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