Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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02/27/2024
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Application #:
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17233699
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Filing Dt:
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04/19/2021
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Publication #:
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Pub Dt:
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08/05/2021
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Inventors:
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Rachid Salik, Cheng-Chi Wu, Wen-Ju Yang, Chin-Chang Hsu, Chien-Wen Chen
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Title:
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Integrated Circuit Layout Validation Using Machine Learning
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Assignment:
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NO. 8, LI-HSIN RD. VI, |
HSINCHU SCIENCE PARK |
HSINCHU, TAIWAN |
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JONES DAY |
250 VESEY STREET |
NEW YORK, 10281-1047 UNITED STATES |
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05/17/2024 11:37 PM
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