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Patent Assignment Abstract of Title
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Total Assignments: 2
Patent #:
4376657
Issue Dt:
03/15/1983
Application #:
06213400
Filing Dt:
12/05/1980
Inventors:
KAZUTOSHI NAGASAWA, SEIGO KISHINO, YOSHIAKI MATSUSHITA, MASARU KANAMORI
Title:
METHOD OF MAKING FAULT-FREE SURFACE ZONE IN SEMICOONDUCTOR DEVICES BY STEP-WISE HEAT TREATING
Assignment: 1
Reel/Frame:
003830/0765Recorded: 12/05/1980Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST.
Assignors:
NAGASAWA KAZUTOSHI
Exec Dt:
11/14/1980
KISHINO SEIGO
Exec Dt:
11/14/1980
MATSUSHITA YOSHIAKI
Exec Dt:
11/14/1980
KANAMORI MASARU
Exec Dt:
11/14/1980
Assignee:
VLSI TECHNOLOGY RESEARCH ASSOCIATION
4-28, MITA 1-CHOME, MINATO-KU
A CORP. OF JAPAN
TOKYO, JAPAN 108
Correspondent:
STAAS & HALSEY
1825 K STREET, N. W.
WASHINGTON, DC 20006
Assignment: 2
Reel/Frame:
005366/0758Recorded: 07/19/1990Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST.
Assignor:
VLSI TECHNOLOGY RESEARCH ASSOCIATION
Exec Dt:
07/02/1990
Assignees:
FUJITSU LIMITED, A CORP. OF JAPAN
1015, KAMIKODANAKA, NAKAHARA-KU, KAWASAKI-SHI,
KANAGAWA-KEN, JAPAN
KABUSHIKI KAISHA TOSHIBA, A CORP. OF JAPAN
72, HORIKAWA-CHO, SAIWAI-KU, KAWASAKI-SHI,
KANAGAWA-KEN, JAPAN
Correspondent:
STAAS & HALSEY
1825 K STREET, N. W.
WASHINGTON, DC 20006

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