Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/12/1988
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Application #:
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06792097
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Filing Dt:
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10/28/1985
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Inventor:
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WEN-YUAN WANG
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Title:
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DUAL FAULT-MASKING REDUNDANCY LOGIC CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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IBM CORPORATION |
PATENT OPERATIONS |
DEPT. 901/BLDG. 300188 |
HOPEWELL JUNCTION, NY., 12533 |
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