Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/15/1990
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Application #:
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07290257
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Filing Dt:
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12/27/1988
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Inventor:
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PAUL D. MADLAND
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Title:
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MEMORY TIMING CIRCUIT EMPLOYING SCALED-DOWN MODELS OF BIT LINES USING REDUCED NUMBER OF MEMORY CELLS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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| 3065 BOWERS AVE. |
| SANTA CLARA, CALIFORNIA 95051 |
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| BLAKELY, SOKOLOFF, TAYLOR AND ZAFMAN |
| 12400 WILSHIRE BLVD., 7TH FLOOR |
| LOS ANGELES, CA 90025 |
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