Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/13/1993
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Application #:
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07757412
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Filing Dt:
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09/10/1991
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Inventors:
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ERIC A. JOHNSON, YING T. LOH, YOSHIKO H. STRUNK, CHUNG S. WANG
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Title:
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A METHOD FOR PRODUCING GATE OVERLAPPED LIGHTLY DOPED DRAIN (GOLDD) STRUCTURE FOR SUBMICRON TRANSISTOR
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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| A CORPORATION OF DE |
| 1109 MCKAY DRIVE |
| SAN JOSE, CALIFORNIA 95131 |
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| VLSI TECHNOLOGY, INC. |
| LEGAL DEPT. |
| 1109 MC KAY DR. |
| SAN JOSE, CA 95131 |
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