Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/18/1994
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Application #:
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07695983
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Filing Dt:
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05/06/1991
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Inventors:
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YOSHINOBU NAKAGOME, EIJI KUME, KIYOO ITOH, HITOSHI TANAKA
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Title:
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HIGH-SPEED SEMICONDUCTOR MEMORY INTEGRATED CIRCUIT ARRANGEMENT HAVING POWER AND SIGNAL LINES WITH REDUCED RESISTANCE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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A CORPORATION OF JAPAN |
6, KANDA SURUGADAI 4-CHOME, CHIYODA |
TOKYO, JAPAN |
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A CORPORATION OF JAPAN |
20-1, JOUSUIHONCHO 5-CHOME, KODAIRA-SHI, |
TOKYO, JAPAN |
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GREGORY E. MONTONE |
ANTONELLI, TERRY, STOUT & KRAUS |
1919 PENNSYLVANIA AVE., STE. 600 |
WASHINGTON, DC 20006 |
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