Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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08/09/1994
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Application #:
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07771001
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Filing Dt:
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10/01/1991
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Inventors:
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KATSURA TAKAMISAWA, YUKIHIRO NISHIGUCHI
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Title:
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MINIMIZING THE PROGRRAMMING TIME IN A SEMICONDUCTOR INTERGRATED MEMORY CIRCUIT HAVING AN ERROR CORRECTION FUNCTION
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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7-1, SHIBA 5-CHOME, MINATO-KU, |
TOKYO, JAPAN |
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WHITHAM & MARHOEFER |
RESTON INTERNATIONAL CENTER |
11800 SUNRISE VALLEY DRIVE |
RESTON, VA 22090 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1753 SHIMONUMABE, NAKAHARA-KU |
KAWASAKI, KANAGAWA 211-8668, JAPAN |
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SUGHRUE MION, PLLC |
2100 PENNSYLVANIA AVENUE, N.W. |
WASHINGTON, DC 20037 |
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