Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/05/1996
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Application #:
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08363062
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Filing Dt:
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12/21/1994
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Inventors:
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DIPANKAR PRAMANIK, VIVEK JAIN, MILIND G. WELING
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Title:
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METHOD IMPROVING INTEGRATED CIRCUIT PLANARIZATION DURING ETCHBACK
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1109 MCKAY DRIVE |
| LEGAL DEPARTMENT, MS/45 |
| SAN JOSE, CALIFORNIA 95131 |
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| VLSI TECHNOLOGY, INC. |
| WILLIAM G. BECKER, ESQUIRE |
| 1109 MCKAY DRIVE |
| LEGAL DEPARTMENT MS-45 |
| SAN JOSE, CA 95131 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1109 MCKAY DRIVE |
| LEGAL DEPARTMENT, MS/45 |
| SAN JOSE, CALIFORNIA 95131 |
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| VLSI TECHNOLOGY, INC. |
| WILLIAM G. BECKER, ESQUIRE |
| 1109 MCKAY DRIVE |
| LEGAL DEPARTMENT, MS-45 |
| SAN JOSE, CA 95131 |
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