Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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05/21/1996
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Application #:
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08281835
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Filing Dt:
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07/28/1994
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Inventor:
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NAOKI MIURA
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Title:
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SEMICONDUCTOR MEMORY CIRCUIT WITH BIT LINE DETECTOR CONTROLLING ACCESS TO DATA BUS LINES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-12, TORANOMON 1-CHOME |
| MINATO-KU, TOKYO, JAPAN |
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| THOMAS LANGER |
| FRISHAUF, HOLTZ, GOODMAN & WOODWARD, P.C |
| 600 THIRD AVENUE, 30TH FLOOR |
| NEW YORK, NY 10016-2088 |
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