Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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08/20/1996
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Application #:
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07849242
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Filing Dt:
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03/11/1992
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Inventor:
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MICHAEL N. MISHELOFF
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Title:
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TIMING MODEL AND CHARACTERIZATION SYSTEM FOR LOGIC SIMULATION OF INTEGRATED CIRCUITS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST.
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A CORP. OF DE. |
1109 MCKAY DRIVE |
SAN JOSE, CALIFORNIA 95131 |
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VLSI TECHNOLOGY INC. |
LEGAL DEPT. |
1109 MC KAY DR. |
SAN JOSE, CA 95131 |
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