Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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12/31/1996
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Application #:
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08524039
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Filing Dt:
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09/06/1995
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Inventors:
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NARAYANAN MEYYAPPAN, TATSUO NAKATO
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Title:
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METHOD OF TREATING SILICON TO OBTAIN THIN, BURIED INSULATING LAYER
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 101 E. 8TH STREET, SUITE 325E |
| VANCOUVER, WASHINGTON 98660 |
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| ROBERT D. VARITZ |
| ROBERT D. VARITZ, P.C. |
| 4155 U.S. BANCORP TOWER |
| 111 S.W. FIFTHAVENUE |
| PORTLAND, OR 97204 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 5-33 KITAHAMA 4-CHOME CHUO-KU |
| OSAKA CITY, OSAKA, JAPAN |
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| ROBERT D. VARITZ, P.C. |
| ROBERT D. VARITZ |
| 380 HARRISON SQUARE |
| 1800 S.W. FIRST AVENUE |
| PORTLAND, OR 97201 |
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Assignment:
3
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-2-1 SHIBAURA MINATO-KU |
| TOKYO 105-8634, JAPAN |
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| ARMSTRONG, WESTERMAN & HATTORI, LLP |
| DONALD W. HANSON |
| SUITE 1000 |
| 1725 K STREET N.W. |
| WASHINGTON, DC 20006 |
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