Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/11/1997
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Application #:
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08341145
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Filing Dt:
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11/16/1994
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Inventor:
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HIDETO HIDAKA
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Title:
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SEMICONDUCTOR MEMORY DEVICE HAVING A HIERARCHICAL BIT LINE STRUCTURE WITH REDUCED INTERFERENCE NOISE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN 100 |
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| LOWE, PRICE, LEBLANC & BECKER |
| STEPHEN A. BECKER |
| 99 CANAL CENTER PLAZA |
| SUITE 300 |
| ALEXANDRIA, VA 22314 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 500 NEWPORT CENTER DRIVE |
| NEWPORT BEACH, CALIFORNIA 92660 |
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| CLAY MCGURK |
| THE LAW OFFICE OF CLAY MCGURK |
| LAGUNA NIGUEL, CA 92607 |
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