Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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07/08/1997
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Application #:
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08426384
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Filing Dt:
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04/21/1995
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Inventors:
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SEIGOU YUKUTAKE, MASAHIRO IWAMURA, KINYA MITSUMOTO, TAKASHI AKIOKA, NOBORU AKIYAMA
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Title:
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LOGIC GATE CIRCUIT AND PARALLEL BIT TEST CIRCUIT FOR SEMICONDUCTOR MEMORY DEVICES, CAPABLE OF OPERATION AT LOW POWER SOURCE LEVELS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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6, KANDA SURUGADAI 4-CHOME CHIYODA-KU |
TOKYO 101, JAPAN |
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ANTONELLI, TERRY ET AL |
GREGORY E. MONTONE |
1300 N. SEVENTEENTH STREET |
SUITE 1800 |
ARLINGTON, VA 22209 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1753 SHIMONUMABE, NAKAHARA-KU |
KAWASAKI-SHI |
KANAGAWA, JAPAN 211-8668 |
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ANTONELLI, TERRY, STOUT & KRAUS, LLP |
1300 N. 17TH STREET, SUITE 1800 |
ARLINGTON, VIRGINIA 22209 |
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