Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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09/09/1997
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Application #:
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08404300
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Filing Dt:
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03/14/1995
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Inventors:
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TAKASHI MIHARA, HIROSHI NAKANO, HIROYUKI YOSHIMORI, SHUZO HIRAIDE
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Title:
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METHOD OF DRIVING FERROELECTRIC GATE TRANSISTOR MEMORY CELL
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 43-2, HATAGAYA 2-CHOME, SHIBUYA-KU |
| TOKYO, JAPAN |
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| FRISHAUF, HOLTZ, GOODMAN, LANGER, ET AL |
| LEONARD HOLTZ |
| 767 THIRD AVENUE |
| 25TH FLOOR |
| NEW YORK, NEW YORK 10017-2023 |
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Assignment:
2
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CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE 4TH INVENTOR OF AND ADD AN ASSIGNEE TO AN ASSIGNMENT RECORDED ON REEL 7912, FRAME 0229
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| 43-2, HATAGAYA 2-CHOME |
| SHIBUYA-KU, TOKYO, JAPAN |
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| 5055 MARK DABLING BOULEVARD, #100 |
| COLORADO SPRINGS, COLORADO 80918 |
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| FRISHAUF, HOLTZ, GOODMAN, ET AL |
| LEONARD HOLTZ |
| 767 THIRD AVENUE, 25TH FLOOR |
| NEW YORK, NY 10017-2023 |
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