Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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12/30/1997
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Application #:
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08370888
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Filing Dt:
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01/10/1995
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Inventors:
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TOYOKAZU NAKAMURA, YASUKO HANAGAMA, TOHRU TSUJIDE, KENJI MOROHASHI
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Title:
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SYSTEM AND METHOD FOR FAULT ANALYSIS OF SEMICONDUCTOR INTEGRATED CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 7-1, SHIBA 5-CHOME, MINATO-KU |
| TOKYO, JAPAN |
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| JANET SCZEPANSKI |
| WHITHAM, CURTIS, WHITHAM ET AL. |
| 11800 SUNRISE VALLEY DRIVE |
| STE. 900 |
| RESTON, VA 22091 |
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Assignment:
2
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| 7-1, SHIBA 5-CHOME, MINATO-KU |
| TOKYO, JAPAN |
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| MR. SEAN MCGINN |
| WHITHAM, CURTIS, WHITHAM & MCGINN |
| 11800 SUNRISE VALLEY DRIVE |
| SUITE 900 |
| RESTON, VA 22091 |
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