Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/27/1998
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Application #:
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08633486
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Filing Dt:
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04/17/1996
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Inventors:
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SHUNZO YAMASHITA, KAZUO YANO, YASUHIKO SASAKI, KOICHI SEKI
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Title:
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LOGIC CIRCUIT SYNTHESIZING METHOD UTILIZING BINARY DECISION DIAGRAM EXPLORED BASED UPON HIERARCHY OF CORRELATION BETWEEN INPUT VARIABLES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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CHIYODA-KU |
6, KANDA SURUGADAI 4-CHOME |
TOKYO, JAPAN |
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FAY, SHARPE, BEALL ETAL |
THOMAS E. BEALL, JR. |
104 EAST HUME AVENUE |
ALEXANDRIA, VA 22301 |
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