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Patent Assignment Abstract of Title
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Total Assignments: 1
Patent #:
5802266
Issue Dt:
09/01/1998
Application #:
08323094
Filing Dt:
10/14/1994
Inventors:
NOBUYASU KANEKAWA, SHOJI SUZUKI, YOSHIMICHI SATO, KOREFUMI TASHIRO, KEISUKE BEKKI et al
Title:
LOGIC CIRCUIT HAVING ERROR DETECTION FUNCTION, REDUNDANT RESOURCE MANAGEMENT METHOD, AND FAULT TOLERANT SYSTEM USING IT
Assignment: 1
Reel/Frame:
008689/0885Recorded: 08/21/1997Pages: 3
Conveyance:
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
Assignors:
KANEKAWA, NOBUYASU
Exec Dt:
09/27/1994
SUZUKI, SHOJI
Exec Dt:
09/27/1994
SATO, YOSHIMICHI
Exec Dt:
09/27/1994
TASHIRO, KOREFUMI
Exec Dt:
09/27/1994
BEKKI, KEISUKE
Exec Dt:
09/27/1994
SATO, HIROSHI
Exec Dt:
09/27/1994
NOHMI, MAKOTO
Exec Dt:
09/27/1994
OHTSUJI, SHINYA
Exec Dt:
09/27/1994
Assignee:
HITACHI, LTD.
4-CHOME, CHIYODA-KU
6, KANDA SURUGADAI
TOKYO 101, JAPAN
Correspondent:
ANTONELLI, TERRY, STOUT ET AL.
DAVID S. LEE
1300 NORTH SEVENTEENTH ST.
SUITE 1800
ARLINGTON, VA 22209

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