Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/01/1999
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Application #:
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08692096
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Filing Dt:
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08/07/1996
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Inventor:
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YUSUKE MATSUNAGA
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Title:
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SYSTEM AND METHOD FOR VERIFYING LOGIC CIRCUIT BASED ON SIGNAL LINE SET AFFECTING INTERNAL SIGNAL
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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KAWASAKI-SHI |
1-1, KAMIKODANAKA, 4-CHOME NAKAHARA-KU |
KANAGAWA 211, JAPAN |
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STAAS & HALSEY |
JAMES D. HALSEY |
700 ELEVENTH STREET, N.W. |
SUITE 500 |
WASHINGTON, DC 20001 |
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