Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
06/29/1999
|
Application #:
|
08686375
|
Filing Dt:
|
07/25/1996
|
|
Inventor:
|
MASAHIKO UEDA
|
|
Title:
|
METHOD FOR DESIGNING PATH TRANSISTOR LOGIC CIRCUIT
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 1006, OHAZA KADOMA |
| KADOMA-SHI, OSAKA, JAPAN 571 |
|
|
|
|
| MARK D. SARALINO |
| 1621 EUCLID AVE., 19TH FLOOR |
| CLEVELAND, OH 44115 |
|
|
Search Results as of:
05/05/2024 05:11 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
