Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/29/1999
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Application #:
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08806686
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Filing Dt:
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02/26/1997
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Inventor:
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TSUKASA MATOBA
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Title:
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SYSTEM FOR SIMULTANEOUSLY WRITING BACK CACHED DATA VIA FIRST BUS AND TRANSFERRING CACHED DATA TO SECOND BUS WHEN READ REQUEST IS CACHED AND DIRTY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 72 HORIKAWA-CHO, SAIWAI-KU |
| KAWASHIKI-SHI, JAPAN |
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| FINNEGAN, HENDERSON, FARABOW ET AL |
| RICHARD V. BURGUJIAN |
| 1300 I STREET, N.W. |
| WASHINGTON, D.C. 20005-3315 |
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