Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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07/13/1999
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Application #:
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08732808
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Filing Dt:
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10/15/1996
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Inventors:
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SHINICHI KUMASHIRO, HIROSHI MIZUNO, YASUHIRO TANAKA, TOSHIYUKI MORIWAKI, YOUICHIROU MAE
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Title:
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METHOD FOR DESIGNING LAYOUT OF SEMICONDUCTOR INTEGRATED CIRCUIT SEMICONDUCTOR INTEGRATED CIRCUIT OBTAINED BY THE SAME METHOD AND METHOD FOR VERIFYING TIMING THEREOF
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1006 OAZA KADOMA, KADOMA-SHI |
| OSAKA, JAPAN 571 |
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| MCDERMOTT, WILL & EMERY |
| EDWARD E. KUBASIEWICZ, ESQ. |
| 1850 K STREET, N.W., SUITE 450 |
| WASHINGTON, D.C. 20006-2296 |
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