Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
11/23/1999
|
Application #:
|
08315619
|
Filing Dt:
|
09/30/1994
|
|
Inventors:
|
TOMOKI NISHINO, MASASHI TAKEDA
|
|
Title:
|
PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A LOGIC CIRCUIT AND A PLURALITY OF INPUT/OUTPUT AMPLIFIER CIRCUITS
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 7-35 KITASHINAGAWA |
| 6-CHOME, SHINAGAWA-KU |
| TOKYO, JAPAN |
|
|
|
|
| HILL, STEADMAN & SIMPSON P.C. |
| LEWIS T. STEADMAN |
| 85TH FLOOR SEARS TOWER |
| 233 S. WACKER DRIVE |
| CHICAGO, IL 60606 |
|
|
Search Results as of:
05/04/2024 07:04 PM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
