Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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12/21/1999
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Application #:
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08773313
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Filing Dt:
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12/24/1996
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Inventors:
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HIROYUKI MORINAKA, HIROSHI MAKINO, KIMIO UEDA, KOICHIRO MASHIKO
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Title:
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SEMICONDUCTOR INTEGRATED CIRCUIT AND CONSUMED POWER REDUCING METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100, JAPAN |
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| OBLON, SPIVAK, MCCLELLAND ET AL. |
| MARVIN J. SPIVAK |
| FOURTH FLOOR |
| 1755 JEFFERSON DAVIS HIGHWAY |
| ARLINGTON, VA 22202 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN 211-8668 |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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