Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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02/15/2000
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Application #:
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08746527
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Filing Dt:
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11/12/1996
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Inventors:
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TAKASHI IPPOSHI, TOSHIAKI IWAMATSU, YASUO YAMAGUCHI
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Title:
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AN ELEMENT ISOLATION STRUCTURE OF A SEMICONDUCTOR DEVICE TO SUPPRESS REDUCTION IN THRESHOLD VOLTAGE OF PARASITIC MOS TRANSISTOR
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100, JAPAN |
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| LOWE, PRICE, LEBLANC & BECKER |
| GENE Z. RUBINSON |
| 99 CANAL CENTER PLAZA, SUITE 300 |
| ALEXANDRIA, VIRGINIA 22314 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1753, SHIMONUMABE, NAKAHARA-KU, KAWASAKI-SHI, |
| KANAGAWA, JAPAN 211-8668 |
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| MCDERMOTT WILL & EMERY LLP |
| 600 THIRTEENTH STREET, N.W. |
| WASHINGTON, DC 20005-3096 |
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