Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/14/2000
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Application #:
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09003500
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Filing Dt:
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01/06/1998
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Inventors:
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MICHINOBU NAKAO, KAZUMI HATAYAMA, JUN HIRANO
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Title:
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METHOD OF ANALYZING LOGIC CIRCIT TEST POINTS, APPARATUS FOR ANALYZING LOGIC CIRCUIT TEST POINTS AND SEMICONDUCTOR INTRGRATED CIRCUIT WITH TEST POINTS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 6-KANDA SURUGADAI 4-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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| ANTONELLI, TERRY, STOUT & KRAUS, LLP |
| GREGORY E. MONTONE |
| 1300 NORTH SEVENTEENTH STREET |
| SUITE 1800 |
| ARLINGTON, VA 22209 |
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