Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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03/21/2000
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Application #:
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08835488
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Filing Dt:
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04/08/1997
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Inventors:
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MIKIHIRO KIMURA, MASAHIRO SEKINE
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Title:
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SEMICONDUCTOR TEST STRUCTURE FOR ESTIMATING DEFECTS AT ISOLATION EDGE AND TEST METHOD USING THE SAME
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
TOKYO 100, JAPAN |
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OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT |
ROBERT F. GNUSE |
FOURTH FLOOR |
1755 JEFFERSON DAVIS HIGHWAY |
ARLINGTON, VA 22202 |
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Assignment:
2
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(ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE RECORDATION DATE OF 11-11-1998 TO 12-01-1998 PREVIOUSLY RECORDED AT REEL 9612 FRAME 0167.
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2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
TOKYO 100, JAPAN |
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OBLON, SPIVAK, MCCLELLAND, MAIER ETAL |
ROBERT F. GNUSE |
1755 JEFFERSON DAVIS HIGHWAY |
FOURTH FLOOR |
ARLINGTON, VIRGINIA 22202 |
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05/09/2024 02:48 AM
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