Patent Assignment Abstract of Title
NOTE:Results display only for issued patents and published applications.
For pending or abandoned applications please consult USPTO staff.
|
Total Assignments:
1
|
|
Patent #:
|
|
Issue Dt:
|
05/09/2000
|
Application #:
|
09427727
|
Filing Dt:
|
10/27/1999
|
|
Inventors:
|
JAMES B. KUO, SHENG-CHE LIU
|
|
Title:
|
0.7V TWO-PORT 6T SRAM MEMORY CELL STRUCTURE WITH SINGLE-BIT-LINE SIMULTANEOUS READ- AND WRITE ACCESS (SBLSRWA) CAPABILITY USING PARTIALLY-DEPLETED SOI CMOS DYNAMIC -THRESHOLD TECHNIQUE
|
|
|
Assignment:
1
|
|
|
|
|
|
|
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
|
|
|
|
|
|
|
|
|
| 18FL, NO. 106, SEC.2 HO-PING E. RD. |
| TAIPEI, TAIWAN R.O.C |
|
|
|
|
| THOMAS, KAYDEN, HORSTEMEYER & RISLEY LLP |
| DANIEL R. MCCLURE |
| 100 GALLERIA PARKWAY, SUITE 1750 |
| ATLANTA, GA 30339 |
|
|
Search Results as of:
05/27/2024 02:54 AM
If you have any comments or questions concerning the data displayed,
contact
PRD / Assignments at 571-272-3350. v.2.6
Web interface last modified:
August 25, 2017 v.2.6
|
