Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/24/2000
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Application #:
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09135055
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Filing Dt:
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08/18/1998
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Inventor:
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SYUZO MURAI
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Title:
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RELIABILTY VERIFICATION DEVICE FOR DETECTING PORTION OF DESIGN THAT MAY CAUSE MALFUNCTION OF SEMICONDUCTOR INTEGRATED CIRCUIT AND ITS VERIFYING METHOD
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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7-1, SHIBA, 5-CHOME, MINATO-KU |
TOKYO, JAPAN |
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MCGINN & GIBB, P.C. |
SEAN M. MCGINN, ESQ. |
1701 CLARENDON BLVD., SUITE 100 |
ARLINGTON, VA 22209 |
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