Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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10/31/2000
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Application #:
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09031209
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Filing Dt:
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02/26/1998
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Inventors:
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HIROAKI IWASHITA, TSUNEO NAKATA
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Title:
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LOGICAL DEVICE VERIFICATION METHOD AND APPARATUS
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 1-1, KAMIKODANAKA, 4-CHOME NAKAHARA-KU, KAWASAKI-SHI |
| KANAGAWA 211-8588, JAPAN |
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| STAAS & HALSEY |
| JAMES D. HALSEY, JR. |
| 700 ELEVENTH STREET, N.W., SUITE 500 |
| WASHINGTON, D.C. 20001 |
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