Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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01/30/2001
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Application #:
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09294171
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Filing Dt:
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04/19/1999
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Inventors:
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CHWAN-YING LEE, TZUEN-HSI HUANG, TSYR-SHYANG LIOU
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Title:
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FABRICATION PROCESS FOR A SINGLE POLYSILICON LAYER, BIPOLAR JUNCTION TRANSISTOR FEATURING REDUCED JUNCTION CAPACITANCE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 195 SEC. 4, CHUNG HSING RD. |
| CHUTUNG, HSINCHU, TAIWAN R.O.C |
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| GEORGE O. SAILE |
| 20 MCINTOSH DRIVE |
| POUGHKEEPSIE, NY 12603 |
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