Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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02/20/2001
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Application #:
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09169275
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Filing Dt:
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10/08/1998
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Inventors:
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ALLEN S. YU, PATRICK K. CHEUNG, PAUL J. STEFFAN
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Title:
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METHOD FOR FORMING GRADED LDD TRANSISTOR USING CONTROLLED POLYSILICON GATE PROFILE
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| P.O. BOX 3453 |
| ONE AMD PLACE |
| SUNNYVALE, CALIFORNIA 94088 |
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| MIKIO ISHIMARU |
| THE LAW OFFICES OF MIKIO ISHIMARU |
| 1046 PINENUT COURT |
| SUNNYVALE, CA 94087 |
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| MIKIO ISHIMARU |
| 1046 PINENUT COURT |
| SUNNYVALE, CA 94087 |
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Assignment:
2
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(ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE NUMBER OF MICROFILM PAGES FROM 4 TO 6 ON REEL 9538, FRAME 406.
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| P.O. BOX 3453 |
| ONE AMD PLACE |
| SUNNYVALE, CALIFORNIA 94088 |
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| THE LAW OFFICES OF MIKIO ISHIMARU |
| MIKIO ISHIMARU |
| 1046 PINENUT COURT |
| SUNNYVALE, CA 94087 |
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