Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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03/27/2001
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Application #:
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09044927
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Filing Dt:
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03/20/1998
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Inventor:
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SHIGENOBU MAEDA
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Title:
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GATE ARRAY AND MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT USING GATE ARRAY
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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CHIYODA-KU |
2-3, MARUNOUCHI 2-CHOME |
TOKYO 100, JAPAN |
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OBLON, SPIVAK, MCCLELLAND, MAIER, ET AL |
JOSEPH A. SCAFETTA, JR. |
FOURTH FLOOR |
1755 JEFFERSON DAVIS HIGHWAY |
ARLINGTON, VIRGINIA 22202 |
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