Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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05/29/2001
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Application #:
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09179178
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Filing Dt:
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10/27/1998
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Inventor:
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KENICHIRO SONODA
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Title:
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METHOD OF SIMULATING AN INTEGRATED CIRCUIT FOR ERROR CORRECTION IN A CONFIGURATION MODEL, AND A COMPUTER-READABLE RECORDING MEDIUM
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Assignment:
1
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INVALID DOCUMENT. SEE RECORDING AT REEL 012293 FRAME 0810. (RE-RECORDED TO CORRECT THE RECORDATION NOTICE)
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT |
| MARVIN J. SPIVAK |
| 1755 JEFF DAVIS HWY., 4TH FLOOR |
| ARLINGTON, VA 22202 |
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Assignment:
2
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(ASSIGNMENT OF ASSIGNOR'S INTEREST) RE-RECORD TO CORRECT THE RECORDATION DATE OF 02/20/2001 TO 02/28/2001, PREVIOUSLY RECORDED AT REEL 11570, FRAME 0121.
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| 2-3, MARUNOUCHI 2-CHOME, CHIYODA-KU |
| TOKYO 100-8310, JAPAN |
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| OBLON SPIVAK MCCLELLAND MAIER & NEUSTADT |
| JOSEPH A. SCAFETTA, JR. |
| 1755 JEFFERSON DAVIS HIGHWAY, 4TH FLOOR |
| ARLINGTON, VA 22202 |
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