Patent Assignment Abstract of Title
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Total Assignments:
1
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Patent #:
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Issue Dt:
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06/19/2001
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Application #:
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09109999
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Filing Dt:
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06/08/1997
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Inventors:
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HAN YOUNG KOH, JEH-FU TUAN, TAK K. YOUNG
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Title:
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METHOD AND SYSTEM FOR RELIABILITY ANALYSIS OF CMOS VLSI CIRCUITS BASED ON STAGE PARTITIONING AND NODE ACTIVITIES
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 700 EAST MIDDLEFIELD ROAD |
| MOUNTAIN VIEW, CALIFORNIA 94043 |
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| BEVER, HOFFMAN & HARMS, LLP |
| 1730 HOLMES STREET |
| BUILDING B |
| LIVERMORE, CA 94550 |
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