Patent Assignment Abstract of Title
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Total Assignments:
3
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Patent #:
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Issue Dt:
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10/30/2001
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Application #:
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09564754
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Filing Dt:
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05/04/2000
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Inventors:
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Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi et al
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Title:
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Semiconductor integrated circuit arrangement fabrication method
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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| MATTINGLY, STANGER & MALUR, P.C. |
| JOHN R. MATTINGLY |
| 1800 DIAGONAL ROAD, SUITE 370 |
| ALEXANDRIA, VIRGINIA 22314 |
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Assignment:
2
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CORRECTIVE COVERSHEET TO CORRECT SERIAL NUMBER PREVIOUSLY RECORDED ON REEL 015409, FRAME 0602.
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| 4-1, MARUNOUCHI 2-CHOME |
| CHIYODA-KU, TOKYO, JAPAN |
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| MATTINGLY, STANGER & MALUR, P.C. |
| JOHN R. MATTINGLY |
| 1800 DIAGONAL ROAD, SUITE 370 |
| ALEXANDRIA, VA 22314 |
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Assignment:
3
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MERGER (SEE DOCUMENT FOR DETAILS).
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| 1753 SHIMONUMABE, NAKAHARA-KU |
| KAWASAKI-SHI |
| KANAGAWA, JAPAN |
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| ANTONELLI, TERRY, STOUT & KRAUS, LLP |
| 1300 N. 17TH STREET, SUITE 1800 |
| ARLINGTON, VIRGINIA 22209 |
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