Patent Assignment Abstract of Title
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Total Assignments:
2
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Patent #:
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Issue Dt:
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11/06/2001
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Application #:
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09331780
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Filing Dt:
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06/24/1999
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Inventors:
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SHUNZO YAMASHITA, KAZUO YANO
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Title:
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LOGIC CIRCUIT INCLUDING COMBINED PASS TRANSISTOR AND CMOS CIRCUIT AND A METHOD OF SYNTHESIZING THE LOGIC CIRCUIT
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Assignment:
1
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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NEW MARUNOUCHI BUILDING |
5-1, MARUNOUCHI 1-CHOME |
CHIYODA-KU, TOKYO 100-8220, JAPAN |
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ANTONELLI, TERRY, STOUT ET AL. |
GREGORY E. MONTONE |
1300 NORTH SEVENTEENTH STREET |
SUITE 1800 |
ARLINGTON, VA 22209 |
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Assignment:
2
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ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS).
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1753 SHIMONUMABE, NAKAHARA-KU |
KAWASAKI-SHI |
KANAGAWA, JAPAN 211-8668 |
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ANTONELLI, TERRY, STOUT & KRAUS, LLP |
1300 N. 17TH STREET, SUITE 1800 |
ARLINGTON, VIRGINIA 22209 |
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